The invention relates to a method for fabricating and checking at least two structures of an electronic circuit in a semiconductor substrate.
Electronic circuits of this type are typically formed as integrated circuits on a wafer, preferably a silicon wafer. The integrated circuits may be formed as dynamic random access memory (DRAM) cells, for example. A wafer contains an areal configuration of a multiplicity of DRAM cells of this type, which are formed as chips. The chip areas of the individual chip form the useful areas of the wafer. The individual useful areas are bordered by scribe lines, so-called kerfs. Electronic circuits that are used to check the functionality and reliability of the electronic circuits on the individual chip areas are situated in the scribe lines.
Chips with standard DRAM cells usually have a configuration of transistors having a specific gate oxide thickness. In order to check these transistors, structurally identical transistors are disposed in the scribe lines. These transistors in the scribe line form monitoring and reliability structures that are used for carrying out predetermined measurement and test steps. Statements about the functionality and reliability of the transistors on the chip areas of the individual chips can be derived from the measurement and test steps.
In order to obtain statistical statements that are as reliable as possible during the measurement and test steps, it is desirable to place the largest possible number of transistors in the scribe lines. However, the maximum number of transistors in the scribe lines is limited by the fact that the chip yield per wafer should be as high as possible. This limits the available area of the scribe lines and hence the number of transistors placed there.
In the case of novel DRAM cells required for RAMBUS chips, for example, transistors having a plurality (preferably two) of different gate oxide thicknesses are required on account of the performance and reliability to be achieved for such elements.
Accordingly, in order to check these structures, transistors having both small and large gate oxide thicknesses have to be provided in the scribe lines in order that the functionality and reliability of both structures can be checked.
In order that, in comparison with standard DRAM cells, for each kind of transistors the same number is available in the scribe lines, the areas of the scribe lines would have to be enlarged, which would lead to an undesirable reduction of the chip areas.
It is accordingly an object of the invention to provide a method for fabricating and checking structures of electronic circuits in a semiconductor substrate that overcomes the above-mentioned disadvantages of the prior art methods of this general type, which ensures that different structures of an electronic circuit in a semiconductor substrate are checked as reliably as possible, without the useful area of the substrate being restricted.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating and checking at least two structures of an electronic circuit in a semiconductor substrate. The method includes using a first mask having a plurality of first parts for defining first useful areas and first scribe lines bordering the first useful areas. The first mask extends over first regions of the semiconductor substrate. First and second structures are produced in the first useful areas according to a predetermined pattern. Further ones of the first structures are produced in the first scribe lines. A second mask having a plurality of second parts is used for defining second useful areas and second scribe lines bordering the second useful area, the second mask extends over second regions of the semiconductor substrate. The first and second structures are produced in the second useful areas according to the predetermined pattern and further ones of the second structures are produced in the second scribe lines. The first structures in the first scribe lines and the second structures in the second scribe lines are used for checking the first and second structures in the first useful areas and the second useful areas.
The method for fabricating and checking at least two structures of an electronic circuit in a semiconductor substrate, teaches the use of a first mask. The first mask defines a configuration of useful areas and scribe lines bordering the latter and extends over first regions of the semiconductor substrate. According to a predetermined pattern, the first and second structures are produced in the useful areas and the first structures are produced in the scribe lines.
The second mask defines a configuration of useful areas and scribe lines bordering the latter and extends over second regions of the semiconductor substrate. According to the predetermined pattern, the first and second structures are produced in the useful areas and the second structures are produced in the scribe lines.
The first structures in the scribe lines of the first regions and the second structures in the scribe lines of the second regions are in each case used for checking the first and second structures in the useful areas.
The basic concept of the invention is that, using the two masks in the respective first or second regions, identically formed first and second structures are produced in the useful areas, but either only first or only second structures are produced in the scribe lines.
In this case, the first and second regions are distributed alternately and preferably in a chessboard-like manner over the entire surface of the semiconductor substrate. In the first regions, only the first structures are disposed in the scribe lines, so that only first structures are checked in these regions, although both first and second structures are situated in the assigned useful areas. Correspondingly, only the second structures are disposed in the second regions, so that only the functionality of the second structures can be checked there, although both first and second structures are situated in the assigned useful areas of the second regions.
By virtue of this configuration, the first and second structures are tested separately in separate regions. One essential advantage is that in each case only one structure of electronic circuits is present in all scribe lines of both regions, with the result that the number of structures in a scribe line can be kept small. Therefore, the area of the scribe lines can be given correspondingly small dimensions and the useful areas can be given correspondingly large dimensions, thereby obtaining a correspondingly high yield in the fabrication of electronic circuits on the semiconductor substrate.
At the same time, the complementary configuration of the first and second structures in the scribe lines of the first and second regions ensures that the reliability and functionality of both structures can be checked with a sufficiently high process dependability. The chessboard-like configuration of the first and second regions is particularly advantageous in this case. In this way, the first and second structures in the respective scribe line are distributed uniformly over the surface of the semiconductor substrate, with the result that the surface of the semiconductor substrate is in each case covered uniformly during the checking of the first and second structures.
In a particularly advantageous manner, the two masks are used for forming the first and second structures only during a technology starting phase. During a technology starting phase for products produced with the semiconductor substrates, there is an increased requirement for measurement and test steps for the products in order to test the reliability of the products to a sufficient extent.
In a product phase following the technology starting phase, there is a comparatively reduced requirement for measurement and test steps.
In this case, instead of using two masks for fabricating the first and second structures, it is possible to use a single modified first mask.
The modified first mask is not divided into first and second parts. Rather, the mask is formed in such a way that the first and second structures are produced in all useful areas. In each case a predetermined number of first and second structures are produced in the scribe lines, with the result that both structures are then tested simultaneously in a scribe line.
In an advantageous embodiment of the invention, the first and second structures are formed by different gate oxide thicknesses of transistors that are preferably used in DRAM memory cells.
In accordance with an added mode of the invention, there is the step of using the first mask for fabricating first transistors having a first gate oxide thickness. The first mask is formed such that a nitrogen implantation is carried out in gate oxide regions of the first transistors prior to an application of a gate oxide layer, which implantation inhibits a growth of the gate oxide layer subsequently applied.
In accordance with another mode of the invention, there is the step of using the second mask for fabricating second transistors having a second gate oxide thickness being greater than the first gate oxide thickness. The second mask is formed in such a way that no nitrogen implantation is carried out in gate oxide regions of the second transistors prior to an application of the gate oxide layer.
In accordance with a further mode of the invention, there is the step of forming the electronic circuits in the semiconductor substrate to be dynamic random access memory (DRAM) structures in a silicon wafer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating and checking structures of electronic circuits in a semiconductor substrate, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.